Silicon Labs /EFR32MG21A010F512IM32 /RTCC_S /CFG

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Interpret as CFG

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (X0)DEBUGRUN 0 (PRECNTCCV0TOP)PRECNTCCV0TOP 0 (CNTCCV1TOP)CNTCCV1TOP 0 (PRESC)CNTTICK 0 (DIV1)CNTPRESC

CNTTICK=PRESC, CNTPRESC=DIV1, DEBUGRUN=X0

Description

No Description

Fields

DEBUGRUN

Debug Mode Run Enable

0 (X0): RTCC is frozen in debug mode

1 (X1): RTCC is running in debug mode

PRECNTCCV0TOP

Pre-counter CCV0 top value enable.

CNTCCV1TOP

CCV1 top value enable

CNTTICK

Counter prescaler mode.

0 (PRESC): CNT register ticks according to configuration in CNTPRESC.

1 (CCV0MATCH): CNT register ticks when PRECNT matches RTCC_CC0_CCV[14:0]

CNTPRESC

Counter prescaler value.

0 (DIV1): CLK_CNT = (RTCC LF CLK)/1

1 (DIV2): CLK_CNT = (RTCC LF CLK)/2

2 (DIV4): CLK_CNT = (RTCC LF CLK)/4

3 (DIV8): CLK_CNT = (RTCC LF CLK)/8

4 (DIV16): CLK_CNT = (RTCC LF CLK)/16

5 (DIV32): CLK_CNT = (RTCC LF CLK)/32

6 (DIV64): CLK_CNT = (RTCC LF CLK)/64

7 (DIV128): CLK_CNT = (RTCC LF CLK)/128

8 (DIV256): CLK_CNT = (RTCC LF CLK)/256

9 (DIV512): CLK_CNT = (RTCC LF CLK)/512

10 (DIV1024): CLK_CNT = (RTCC LF CLK)/1024

11 (DIV2048): CLK_CNT = (RTCC LF CLK)/2048

12 (DIV4096): CLK_CNT = (RTCC LF CLK)/4096

13 (DIV8192): CLK_CNT = (RTCC LF CLK)/8192

14 (DIV16384): CLK_CNT = (RTCC LF CLK)/16384

15 (DIV32768): CLK_CNT = (RTCC LF CLK)/32768

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